New Lattice ispLEVER 4.2 Design Tool Suite Now Available; Increased Performance, Dozens of New Features, Using Fewer Computing Resources

HILLSBORO, Ore.—(BUSINESS WIRE)—Nov. 15, 2004— Lattice Semiconductor Corporation (NASDAQ:LSCC) today announced the immediate availability of its next generation ispLEVER(R) programmable logic design tool suite. The ispLEVER 4.2 release is a comprehensive upgrade and enhancement of the design tool suite's performance and functionality. FPGA Fmax performance has been increased by an average 22% and map, place and route runtimes have been reduced by 24% for a typical design, lessening the demand on computing resources. Enhancements include an I/O Assistant for efficient placement of mixed I/O types, the addition of new Power Calculator and ispTRACY(TM) Logic Analyzer tools, a new Project Creation Wizard, major upgrades in static timing analysis, floorplanning and DSP design, and a significantly faster and more fully featured ModelSim(R) Simulator from Mentor Graphics. The ispLEVER design tools support all Lattice digital programmable logic devices, including the new LatticeECP-DSP(TM) ("EConomyPlusDSP") and LatticeEC(TM) ("EConomy") FPGA device families, and provide all the features required to develop a design from concept to programmed device.

"The ispLEVER 4.2 suite delivers unprecedented levels of performance, functionality, and ease-of-use to our customers," said Lattice vice president of software Chris Fanning. "LatticeEC and LatticeECP-DSP performance has achieved industry leading standards for low-cost FPGA solutions, and the design suite's runtime and overall system performance have been substantially upgraded to further streamline FPGA design. These performance improvements, coupled with a multitude of new features and improved ease-of-use, make ispLEVER 4.2 a very powerful design tool suite," Fanning concluded.

Industry's Leading EDA Synthesis and Simulation Tools Included in ispLEVER 4.2

The ispLEVER 4.2 design tools include the latest synthesis and simulation tools from industry leaders Mentor Graphics and Synplicity. "Lattice continues to raise the bar for programmable logic tools by providing our customers the industry's most advanced synthesis and simulation tools as standard features and at no additional charge," said Stan Kopec, Lattice vice president of corporate marketing. "We work continuously with our partners to develop the highest level of design tool support for our new technologies, even as we refine the performance of our existing tools."

The Mentor Graphics Leonardo(R)Spectrum synthesis product is standard and fully integrated into the ispLEVER 4.2 push-button design flow. Further, the performance of the Mentor Graphics ModelSim(R) 6.0 tool has significantly reduced simulation times, increasing productivity and improving design time-to-market. "This release of Lattice's ispLEVER design tools includes the industry leading ModelSim and LeonardoSpectrum products, enabling powerful design flow and productivity benefits for customers targeting today's increasingly complex FPGA devices. Mentor Graphics and Lattice engineering teams collaborate closely to continue to drive that power and performance ever higher," said Simon Bloch, General Manager, Design Creation and Synthesis Division, Mentor Graphics. Lattice also plans to offer Mentor's Precision(R) RTL synthesis tool to customers later this year.

The ispLEVER 4.2 tool suite also includes Synplicity's Synplify(R) 7.7 as a standard feature. "Synplify 7.7 includes several significant enhancements designed to boost the performance of Lattice silicon," said Joe Gianelli, Synplicity Vice President of Business Development. "We've focused our efforts on the new LatticeECP-DSP and LatticeEC FPGA device families, and have achieved faster designs than ever before."

Expanded Support for the Newest LatticeECP-DSP and LatticeEC Devices

Design support is now available for the newest members of the LatticeECP-DSP and LatticeEC FPGA architectures, the LatticeECP6 and LatticeEC6. The ispLEVER 4.2 tool suite also adds to the breadth of the ispLEVER blockset for Simulink(R) functions targeting the LatticeECP-DSP architecture. These blocks can be used to build DSP solutions in the MATLAB(R)/Simulink design environment, available separately from The MathWorks.

Design support for the LatticeECP/EC FPGAs has also been expanded to include the Lattice ispTRACY Logic Analyzer tool. Using ispTRACY, the designer can probe and analyze signal activity in the internal nodes of a physical FPGA during operation on a board.

New Features Boost User Productivity

The Lattice ispLEVER 4.2 tool suite includes many new tools and enhancements that make the design process more efficient and effective:

-- I/O Assistant: ispLEVER now allows the user to define the FPGA I/O structure and perform I/O design rule checking early in the design process, allowing the user to make critical I/O placement decisions prior to place and route activities. This ability is particularly valuable for larger projects where design teams must define their I/O strategies for multiple modules early in the design process.

-- Project Wizard: Creating a new ispLEVER design project is now a simple process. The Project Wizard helps a user become productive quickly, and ensures that new design projects are initiated efficiently.

-- Constraint/Preference options: New Lattice-specific HDL design preference options are available in ispLEVER 4.2, providing users more alternatives to choose from to help them optimize their logic in Lattice FPGA architectures.

-- Spreadsheet Export of Preferences: Design preferences, such as I/O assignments, can now be exported in a CSV (Comma Separated Value) format for easy manipulation in spreadsheet programs. This supports the easy transfer of FPGA design schematic models for use in printed circuit board design tools.

-- Easy access to IP Core evaluations: Lattice provides evaluation versions of all IP core netlists to help users quickly determine how a Lattice IP core can accelerate their design. Now, these evaluation IP cores can be downloaded using a simple button in the ispLEVER Module/IP Manager tool.

-- Online help, error messaging and documentation have been significantly enhanced, making the design tools initially easier to learn and use as well as improving ongoing design efficiency and productivity.

A comprehensive list of ispLEVER 4.2 enhancements may be viewed on-line at http://www.latticesemi.com/software.

Availability and pricing

The ispLEVER 4.2 design tools are available now in a variety of PC-, UNIX- and LINUX-based configurations. The ispLEVER tools support all Lattice FPGA, FPSC, ispXPLD(TM), CPLD, GDX(TM) and GAL(R) products in an integrated, easy-to-use design platform. List prices begin at $995. Customers with current maintenance agreements will receive the ispLEVER 4.2 upgrade at no charge.

About Lattice Semiconductor

Lattice Semiconductor Corporation designs, develops and markets the broadest range of Field Programmable Gate Arrays (FPGA), Field Programmable System Chips (FPSC) and high-performance ISP Programmable Logic Devices (PLD), including Complex Programmable Logic Devices (CPLD), Programmable Analog Chips (PAC(TM)), and Programmable Digital Interconnect (GDX). Lattice also offers industry leading SERDES products. Lattice is "Bringing the Best Together" with comprehensive solutions for today's system designs, delivering innovative programmable silicon products that embody leading-edge system expertise.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communications, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037. For more information about Lattice Semiconductor Corporation, visit http://www.latticesemi.com.

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our third party software suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company's Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), GAL, GDX, ispLEVER, ispTRACY, ispXPLD, LatticeEC, LatticeECP, LatticeECP-DSP, PAC and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Other product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

Lattice Semiconductor Corporation
Brian Kiernan, 503-268-8739 
Fax: 503-268-8193 
brian.kiernan@latticesemi.com